The present invention relates to a semiconductor device, and more particularly to a technique which is useful when applied to a semiconductor device such as a multiport SRAM (Static Random Access Memory).
As an example, in Japanese Unexamined Patent Publication No. 2004-335535 (hereafter referred to as Patent Document 1), there is described a multiport memory of SRAM configuration having a layout such that a word line corresponding to a first port and a word line corresponding to a second port are disposed alternately. According to the above configuration, noise can be reduced without increasing a memory cell area because it is possible to avoid such a situation that coupling noise is simultaneously induced to a word line from the word lines disposed on both sides of the word line concerned.
Also, in Japanese Unexamined Patent Publication No. 2004-86970 (hereafter referred to as Patent Document 2), in regard to a bit line A for port A and a bit line B for port B coupled to a dual port DRAM cell, there is described a dual port DRAM configured to have timing to amplify the bit line A different from timing to amplify the bit line B. According to the above configuration, it is possible to prevent crosstalk noise between adjacent bit lines, even when the bit line A and the bit line B are disposed alternately in an open bit structure. Additionally, in regard to word lines, there is shown a configuration having a word line for port A alternately disposed with a word line for port B.
Further, according to Japanese Unexamined Patent Publication No. 2002-197866 (hereafter referred to as Patent Document 3), in a three-port RAM having two pairs of bit lines and a readout line for display being coupled to an SRAM memory cell, there is shown a configuration in which the readout line for display is disposed between either one pair out of the two pairs of bit lines. With the above configuration, it is possible to cancel noise in the readout line for display because complementary coupling noise is induced from the bit lines on both sides of the above readout line. Additionally, in regard to word lines, there is shown a configuration in which a word line for a first port, a word line for a second port and a word line for display readout are repetitively disposed in that order.
FIG. 20 shows a circuit diagram of an exemplary configuration of a multiport memory having been studied as a premise of the present invention. The multiport memory shown in FIG. 20 has a configuration as described in Patent Document 1 and Patent Document 2, in which a word line WLA for port A and a word line WLB for port B are disposed alternately at a pitch d4 which is kept equal between WLA and WLB. Using such the configuration, as described in Patent Document 1, when attention is directed to a word line WLB2 as an example, the word lines WLA1, WLA2 disposed on both sides of WLB2 do not simultaneously rise, and therefore it is possible to reduce coupling noise induced on WLB2.
However, from a different point of view, the exemplary configuration shown in FIG. 20 is configured to have a word line WLA (or WLB) for port A (or port B) sandwiched by word lines WLB (or WLA) for port B (or port A), and therefore, there is a possible problem caused by interference between different ports. FIG. 21 shows an explanatory diagram illustrating one example of operation waveforms between different ports and in an identical port. FIG. 22 shows an explanatory diagram illustrating one example of a trouble due to interference between ports.
In the multiport memory, normally, different ports are operated asynchronously. Therefore, as shown in FIG. 21, mutually neighboring word lines for a first port (port A) and for a second port (port B) as an example may be activated or deactivated at arbitrary timing in an identical cycle. If the above situation occurs, as shown in FIG. 22 for example, when the activation timing of the word line for the first port and the deactivation timing of the word line for the second port coincides, a delay may possibly be produced in the rise time (or fall time) of the waveform because of mutually affecting interference. On the other hand, as shown in FIG. 21, such the problem does not occur because mutually neighboring word lines of an identical port (the first port here) are not activated or deactivated simultaneously. Although the word line is taken as an example in the above description, the similar problem accompanying asynchronous operation may occur in regard to mutually neighboring bit lines for different ports, and in regard to other signal lines also.
Further, as described in Patent Document 1 etc., when there are mutually neighboring word lines for an identical port, it is necessary to consider about an influence of coupling noise given from one word line to the other, needless to say. However, in principle, the signals (word lines, bit lines and signal lines) for an identical port are never activated or deactivated simultaneously in an identical cycle, as illustrated in FIG. 21. Therefore, in the practical design, it is possible to sufficiently predict the degree of influence thereof, and it is possible to easily secure a necessary noise margin by the design. On the other hand, in regard to signals for different ports, activation and deactivation are made mutually asynchronously and at arbitrary timing (in other words, there are infinite number of combinations in the phase relation between the first port signals and the second port signals in the example shown in FIG. 21), and therefore, it is difficult to sufficiently predict the degree of mutual interference. Accordingly, in the case of signals for different ports, it is desirable to secure a relatively larger noise margin, as compared with the case of signals for an identical port.